1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device preferable for flattening of an interlayer film over interconnects having a large surface area, and to a method for manufacturing such a semiconductor device.
2. Background of the Invention
In the past, in a semiconductor device having a multilayer interconnect structure, because a step occurring in the lower interconnect layer made it difficult to form a high-reliability upper interconnect layer, there was an important need to flatten the surface of the interlayer film.
For this reason, when manufacturing a semiconductor device, a manufacturing process such as shown in FIG. 4, was generally used.
Specifically, an insulation film 1 was grown on a semiconductor substrate (not shown in the drawing) and a lower interconnects 2 were formed thereover.
Then, a bias oxide film 3 was grown over the insulation film 1 onto which was formed the lower interconnects 2 (FIG. 4(A)).
After the above steps, chemical mechanical polishing (CMP) was used to remove the surface of the bias oxide film 3 (FIG. 4(B)), thereby making the upper surface of the bias oxide film 3 flat.
Next, a connecting through hole 4 through the entire bias oxide film 3 and reaching the lower interconnect layer 2 is formed, after which an upper interconnect layer 9 is formed thereover (FIG. 4(C)).
If the surface area of the lower interconnect layer is large, however, the surface area of the bias oxide film 3 formed thereover will also be large, the result being that, in the process step whereby CMP is used to remove the bias oxide film 3, it is difficult to remove the bias oxide film 3.
For this reason, there are protrusions on the upper surface of the bias oxide film 3, this resulting in an overall global step at the chip level.
If the surface area of the lower interconnect layer 2 is large, one approach that is used is that of removing the center part of the lower interconnect layer 2 so as to reduce the surface area of the bias oxide film 3 on the lower interconnect layer 2, thereby facilitating the removal of the bias oxide film 3 formed on the lower interconnect layer 2 using CMP.
Using the above-noted method, by making efficient use of the sputtering effect that occurs when the bias oxide film 3 is grown, the amount of bias oxide film 3 removed by CMP is reduced, so that if the lower interconnect layer 2 has a large surface area, it is possible to reduce the step on the upper surface of the bias oxide film 3.
When the center part of the lower interconnect layer 2 is removed, however, there is a reduction in the level of integration of the lower interconnect layer.
For this reason, in order to achieve reliability in the lower interconnect layer, one method that can be envisioned is that of widening the pitch of the lower level interconnects.
However, when the center part the lower interconnect layer is removed but the interconnect pitch on the lower interconnect layer is not widened, because of a reduction in the cross-sectional area of the lower layer of interconnects, the reliability of the interconnects in the semiconductor device is reduced.
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which flattens the interlayer insulation film without removing the center part of the lower interconnect layer, and a semiconductor device that is manufactured according to this method, thereby solving the above-noted problems inherent in the prior art.
In order to achieve the above-noted object, the present invention basically has the following technical conception and in that a first aspect of the present invention provides a semiconductor device which comprises a first interconnect, a second interconnect provided in opposite to the first interconnect, and an insulation film provided between the first and second interconnects, wherein the first and second interconnects are connected to each other via a plurality of metal members each of which being provided inside of each one of a plurality of connecting via holes disposed in the insulation film, respectively.
And further, in that a second aspect of the present invention provides a method for manufacturing a semiconductor device, comprising, a step of growing a first insulation film on a semiconductor substrate, a step of forming a first interconnect on the first insulation film, a step of growing a second insulation film on the first insulation film, including the first interconnect, a step of providing a first connecting via hole in the insulation film and disposed at a position closed to an edge part of the first interconnect and a second connecting via hole in the insulation film and disposed at the center part thereof, a step of growing a metal film on the second insulation film, and a step of removing the metal film using chemical and mechanical polishing.